Flash memories are high-density nonvolatile semiconductor memories offering fast access times. Compared to other nonvolatile semiconductor memories such as EPRPMs or EEPROMs, flash memories are most suitable for applications wherein frequent write and read operations are expected. With the rapid growth of digital cameras and the desire for light-weight notebook PCs, the demand for flash memories even higher densities are ever increasing.
Currently, flash memories are often made by the conventional self-aligned ETOX (electron tunnel oxide) technology. However, it has been observed that the ETOX flash memories can experience an over-erase problem, which results in an increased negative threshold voltage after the erase operation, if the erase operation is not properly designed or if its is improperly performed. When such over-erase problem occurs, positive charges will accumulate under the floating gate, causing the cell threshold voltage to become more negative. Furthermore, when over-erase occurs, cells that are affected will be normally ON during the standby state after erase, causing higher standby or leakage current in the cells.
In order to overcome this problem, several erase schemes and cell structures have been proposed. One of the most promising designs is to use a split gate structure to avoid the over-erase problem in flash memory operation.
FIG. 1 is an illustrative schematic diagram showing the structure of a conventional split gate cell. One of the advantages of a split gate cell is that one part of the channel is controlled by the control gate directly, and the other part is controlled by the floating gate, thus the name split-gate is obtained. When the over-erase occurs in the floating gate, only the portion of the channel under the floating gate will be normally ON and the portion of the channel underneath the control gate remains unaffected. Since the two channels underneath the floating gate and the control gate, respectively, are connected in series, the cell threshold voltage can be maintained positive without introducing large standby current.
FIGS. 2A through 2C schematically show the main steps of the process of fabricating split gate flash memory. FIG. 2A shows that, after field oxidation, a tunnel oxide 1 is grown on a substrate 10, followed by the deposition of first polysilicon layer 2. Then, an inter-poly dielectric layer 3 is formed on the first polysilicon layer 2, which is followed by the deposition of the second polysilicon layer 4.
FIG. 2B shows that a control gate pattern is defined and the second polysilicon layer 4 is etched with the aid of a photoresist 5 to form the control gate 6. FIG. 3C shows that, after the control gate 6 is formed, a second polysilicon etch, which is self-aligned to the control gate, is applied to etch the remaining first polysilicon layer 2 exposed on the substrate surface to form a floating gate 7. This forms a split gate structure comprising a floating gate 7 and a control gate 6 both are formed on the substrate 10 above the tunnel oxide 1 and separated by an inter-poly dielectric layer 3. After source/drain implantation to form source 8 and drain 9, a split gate device is formed as shown in FIG. 1.
One of the main drawbacks of split-gate memories is that, because of the need for the addition channel required to provide direct control for the control gate, under the conventional technology, their size will be about 50% greater than that of the self-aligned ETOX flash memory cell. In order to minimize the increase in the cell size, it is highly desirable to make floating gate as short as possible. However, the minimum length of the floating gate is dictated by the dimensional precision of the photolithography technology. Using the conventional photolithography technology, the size of the split-gate cells cannot be scaled down to the same extent as that of the self-aligned ETOX flash memory cells. Moreover, during the process stop of self-aligned etching of the first polysilicon layer to form the floating gate, extensive over-etch may occur on the region that is not covered by the first polysilicon layer, resulting in possible silicon attack. To avoid such over-etch problem, a stricter process requirement such as extremely high oxide to silicon selectivity is often required for the floating gate etch. This leads to substantially reduced process margins (i.e., rooms for error), reduced yield rate, and increased process cost.
Several prior art processes maybe utilized to prepare split-gate semiconductors with reduced dimensions. They are briefly summarized below. U.S. Pat. No. 5,270,234 discloses a method for fabricating deep submicron transistors which employs only optical lithography and involves the formation of a relative wide aperture using optical techniques. In the process disclosed in the '234 patent, an aperture is formed in a polished layer having a dimension that is considerably larger than the final channel width and within the limits of the lithography. Sidewalls are formed within the aperture in a controllable manner to determine the final channel width of the transistor. The thickness of the sidewalls is maintained during the fabrication process by the use of a two-component sidewall and a selective etch, so that the etching process that determines the final channel dimension does not change the sidewall thickness. The process disclosed in the '234 may have some technical but it is relatively complicated and may not be cost effective.
U.S. Pat. No. 5,374,575 discloses a method for fabricating LDD MOS transistors having a lightly doped drain structure capable of simplifying the fabrication and improving characteristics of the transistor. In a highly integrated system, such as the submicron system, a high electric field may occur at edge portions of the gate electrode causing the generation of hot carriers. The hot carriers serve to degrade the operation characteristic of MOS transistors and reduce the life thereof. The '375 illustrates the importance of having a well defined dimension for the gate electrode; however, it does not teach or suggest method which will allow MOS manufacturers to relax the dimensional precision requirement of lithophotography technique when fabricating submicron MOS transistors.
U.S. Pat. No. 5,538,913 discloses a process for fabricating submicron MOS transistor devices with a full-overlap lightly-doped drain. With the process disclosed in the '913 patent, the gate electrode comprises a conducting layer and a pair of conducting sidewall spacers, and a p-type diffusion region is formed by ion implantation between and below the pair of conducting sidewall spacers to prevent punch-through of the channel region. The MOS transistor fabricated from the '913 has a gate electrode of uniform width.
Because of the importance of flash memories in consumer electronics, it is highly desirable that an improved method be developed which will be able to utilize the currently existing technology so as to allow IC manufacturers to fabricate flash memories with improved performance and reduced size while deferring the need for expensing new capitals.